(1) Field of the Invention
The present invention relates to an A/D conversion apparatus, and especially relates to an A/D conversion apparatus that includes a plurality of channels and has a sequential conversion function.
(2) Description of the Related Art
With the development of inverter control technology in recent years, various motor drive control methods have been proposed.
For position sensorless control in the case of driving a sinusoidal motor, a method of providing a motor current sensor to thereby omit a position sensor for detecting a rotor position of the motor is conventionally known. In the position sensorless control, a voltage drop in the motor is calculated from a voltage applied to the motor, a motor current detected by the motor current sensor, and a motor constant, and a counter electromotive voltage is estimated from the calculated voltage drop. The rotor position is estimated based on the estimated counter electromotive voltage, and the motor is controlled accordingly.
Moreover, due to relatively high costs of motor current sensors, a motor current sensorless control technique that does not use a motor current sensor has been developed, too.
A feature of the motor current sensorless control technique is that a current value flowing through a DC shunt resistor which is conventionally provided for overcurrent protection of an inverter is used instead of a motor current value obtained from a motor current sensor.
In the motor current sensorless control technique, the current value flowing through the DC shunt resistor is amplified in a circuit other than an overcurrent detection circuit, and the amplified current value is taken in an A/D converter in a microcomputer, without involving an external circuit. After the amplified current value is taken in the microcomputer, an operation is performed according to a predetermined current-carrying pattern and rule, as a result of which a motor current is reproduced from the DC current flowing through the shunt resistor.
Against the backdrop of the demand for cost reductions of motor drive control apparatuses, motor current sensorless control has been increasingly adopted. One of the motor current sensorless control methods for sinusoidal motors is a three-shunt sensorless sinusoidal motor drive control method that detects three phases of a sinusoidal motor current using three shunt resistors.
The following describes the three-shunt sensorless sinusoidal motor drive control method, as an example motor current sensorless control technique that does not use a motor current sensor.
FIG. 1 is a block diagram showing a structure of a three-shunt sensorless sinusoidal motor drive control apparatus 900.
As shown in FIG. 1, the three-shunt sensorless sinusoidal motor drive control apparatus 900 includes a sinusoidal drive three-phase motor 905, a motor control power module 906, a motor control microcomputer 907, three shunt resistors 908, a motor current amplification circuit 909, and three A/D converters 911, 912, and 913.
A motor current for driving the sinusoidal drive three-phase motor 905 is controlled by changing ON/OFF states of switching elements included in the motor control power module 906 using a six-phase Pulse Width Modulation (PWM) signal outputted from the motor control microcomputer 907. The motor current for driving the sinusoidal drive three-phase motor 905 is detected by amplifying currents flowing through the three shunt resistors 908 by the motor current amplification circuit 909, inputting the amplified currents into the motor control microcomputer 907, and converting the amplified currents inputted into the three A/D converters 911, 912, and 913 in the motor control microcomputer 907 from analog to digital.
The motor control microcomputer 907 controls the output of the six-phase PWM signal using the detected motor current.
By repeating the control operation as described above, the three-shunt sensorless sinusoidal motor drive control apparatus 900 creates a desired motor drive state.
FIG. 2 shows a PWM timer signal in the motor control microcomputer 907, a PWM signal output waveform of the motor control power module 906, and a timing section for obtaining the motor current.
As shown in FIG. 2, the motor current for driving the sinusoidal drive three-phase motor 905 can be correctly obtained in a section during which an upper arm of the PWM signal of the motor control power module 906 is OFF and a lower arm of the PWM signal of the motor control power module 906 is ON (this section is hereafter referred to as “motor current obtainment timing section”). Note here that when the lower arm of the PWM signal of the motor control power module 906 for driving the sinusoidal drive three-phase motor 905 is ON, the upper arm of the PWM signal of the motor control power module 906 is always OFF.
Since the three-shunt sensorless sinusoidal motor drive control apparatus 900 shown in FIG. 1 includes three A/D converters, the three phases of the motor current for driving the sinusoidal drive three-phase motor 905 can be obtained simultaneously. Therefore, a time required for obtaining these three phase motor currents for driving the sinusoidal drive three-phase motor 905 is only an A/D conversion period corresponding to one phase in a motor current obtainment timing section during which the lower arm of the PWM signal of the motor control power module 906 is ON.
However, the demand for cost reductions of motor drive control apparatuses is even more growing in recent years. In view of this, instead of assigning the plurality of A/D converters 911, 912, and 913 to one sinusoidal drive three-phase motor to perform motor current detection for three phases simultaneously in the above three-shunt sensorless sinusoidal motor drive control apparatus 900, the use of the following A/D conversion apparatus has been proposed. The A/D conversion apparatus assigns one A/D converter to one sinusoidal drive three-phase motor, and performs motor current detection for three phases sequentially, to thereby reduce in cost of the motor drive control apparatus (for example, “TMS320LF/LC240xA DSP Controllers Reference Guide”, Literature Number: SPRU357C, Revised May 2006 (hereafter, “Non-patent Reference 1”)).
The A/D conversion apparatus described in Non-patent Reference 1 includes a plurality of input/output channels, and has a sequential conversion function of sequentially performing A/D conversion in an order of numbers assigned to the plurality of input channels. This being so, by replacing the A/D converters 911, 912, and 913 in the three-shunt sensorless sinusoidal motor drive control apparatus 900 shown in FIG. 1 with one A/D conversion unit described in Non-patent Reference 1, motor current detection for three phases can be performed sequentially.
The following describes a three-shunt sensorless sinusoidal motor drive control apparatus that performs motor current detection for three phases sequentially in an A/D conversion unit having one A/D converter, with reference to drawings.
FIG. 3 is a block diagram showing a structure of an A/D conversion unit 920 that performs motor current detection for three phases sequentially. As shown in FIG. 3, the A/D conversion unit 920 includes a plurality of input channels ADch0 to ADch5, a multiplexer 9200, an A/D converter 9201, a demultiplexer 9202, a control unit 9203, and a register unit 9204.
The plurality of input channels ADch0 to ADch5 are each given a channel number. Hereafter, the channel numbers assigned to the plurality of input channels ADch0 to ADch5 are respectively denoted by ADch0 to ADch5, for ease of explanation. At least two input channels out of the plurality of input channels ADch0 to ADch5 receive input of analog signals obtained by amplifying current values detected in the shunt resistors 908, and output the analog signals to the multiplexer 9200.
The multiplexer 9200 selects one of the plurality of input channels ADch0 to ADch5, and outputs an analog input signal from the selected input channel to the A/D converter 9201.
The A/D converter 9201 converts the analog signal from the input channel selected by the multiplexer 9200 to a digital signal, and outputs the digital signal to the demultiplexer 9202.
The demultiplexer 9202 selects one of a plurality of output registers, and outputs the digital signal generated as a result of the conversion by the A/D converter 9201, to the selected output register.
The control unit 9203 controls the multiplexer 9200, the A/D converter 9201, and the demultiplexer 9202. The control unit 9203 causes the multiplexer 9200 to select one of the plurality of input channels ADch0 to ADch5, and output an analog signal to the A/D converter 9201. The control unit 9203 causes the A/D converter 9201 to convert the analog signal from the input channel selected by the multiplexer 9200 to a digital signal, and output the digital signal to the demultiplexer 9202. The control unit 9203 causes the demultiplexer 9202 to select one of the plurality of output registers, and output the digital signal received from the A/D converter 9201 to the selected output register.
The register unit 9204 includes a sequential A/D conversion start channel setting register 9205 and a sequential A/D conversion end channel setting register 9206. The register unit 9204 also includes a sequential A/D conversion reference start channel setting register 9210 and a sequential A/D conversion reference end channel setting register 9211, which are used for determining an order and range (hereafter referred to as “sequential A/D conversion reference loop”) of channel numbers of input channels that can be selected by the multiplexer 9200.
On the other hand, the sequential A/D conversion start channel setting register 9205 and the sequential A/D conversion end channel setting register 9206 are used for determining a range of channel numbers of input channels that are to be selected by the multiplexer 9200 in the order of channel numbers of the sequential A/D conversion reference loop. That is, a sequential A/D conversion loop of input channels to be selected by the multiplexer 9200 is determined as “sequential A/D conversion start channel→ . . . →sequential A/D conversion end channel→sequential A/D conversion start channel→ . . . ”.
Input channels of channel numbers from a channel number, such as ADch1, set in the sequential A/D conversion start channel setting register 9205 to a channel number, such as ADch3, set in the sequential A/D conversion end channel setting register 9206 are selected by the multiplexer 9200 in an order of the channel numbers, and analog signals inputted into the selected input channels are outputted to the multiplexer 9200.
FIGS. 4A and 4B are explanatory views showing a sequential conversion operation of sequentially performing A/D conversion in the A/D conversion unit 920.
FIG. 4A shows a sequential A/D conversion reference loop defining an order and range of channel numbers of input channels that can be selected by the multiplexer 9200, in the case when the sequential A/D conversion reference start channel setting register 9210 is set to the channel number ADch0 and the sequential A/D conversion reference end channel setting register 9211 is set to the channel number ADch5.
As shown in FIG. 4A, the sequential A/D conversion reference loop (ADch0→ADch1→ADch2→ADch3→ADch4→ADch5→ . . . ) that starts with the channel number ADch0 and ends with the channel number ADch5 is determined according to the settings of the sequential A/D conversion reference start channel setting register 9210 and the sequential A/D conversion reference end channel setting register 9211.
This indicates that the A/D conversion unit 920 sequentially performs conversion in increasing order of channel number.
FIG. 4B shows a sequential conversion operation of sequentially performing A/D conversion in the A/D conversion unit 920, in the case when the sequential A/D conversion start channel setting register 9205 is set to the channel number ADch1 and the sequential A/D conversion end channel setting register 9206 is set to the channel number ADch3.
Since the A/D conversion unit 920 sequentially performs A/D conversion in increasing order of channel number, a sequential A/D conversion loop (ADch1→ADch2→ADch3→ADch1→ . . . ) that starts with the channel number ADch1 and ends with the channel number ADch3 is determined according to the settings of the sequential A/D conversion start channel setting register 9205 and the sequential A/D conversion end channel setting register 9206.
In the three-shunt sensorless sinusoidal motor drive control apparatus 900 that performs motor current detection for three phases sequentially in the above A/D conversion unit 920 having one A/D converter 9201, the three phase motor currents detected by the shunt resistors 908 are amplified and the amplified current values are inputted into the A/D conversion unit 920 as analog input signals. It is assumed here that the analog input signals are inputted into the input channels ADch1, ADch2, and ADch3 in the A/D conversion unit 920.
In the A/D conversion unit 920, the three phase motor currents for driving the sinusoidal drive three-phase motor 905 can be correctly obtained through the sequential conversion of the three input channels ADch1, ADch2, and ADch3, in accordance with the above setting shown in FIGS. 4A and 4B.
In other words, by using an A/D conversion apparatus that includes a plurality of channels and has a sequential conversion function, motor current detection for three phases can be performed sequentially with one A/D converter.
However, in the case of performing motor current detection for three phases sequentially using one A/D converter, it takes three times as long as in the case of performing motor current detection using three A/D converters. Which is to say, in the case when three A/D converters are provided, the time required for obtaining the three phase motor currents for driving the sinusoidal drive three-phase motor 905 is only an A/D conversion period corresponding to one phase in a motor current obtainment timing section during which the lower arm of the PWM signal of the motor control power module 906 is ON. On the other hand, in the case when motor current detection for three phases is performed sequentially using one A/D converter, the time required for obtaining the three phase motor currents is an A/D conversion period corresponding to three phases in a motor current obtainment timing section during which the lower arm of the PWM signal of the motor control power module 906 is ON.
In view of this, based on a known relation that one of the three phase motor currents for driving the sinusoidal drive three-phase motor 905 can be calculated from the other two phase motor currents, a motor control apparatus that uses a two-phase selection control method of detecting two phase motor currents from the shunt resistors 908 to thereby obtain the three phase motor currents has been proposed (see Japanese Unexamined Patent Application Publication No. 2003-284374 (hereafter, “Patent Reference 1”)).
As noted above, in the three-shunt sensorless sinusoidal motor drive control apparatus 900 provided with an A/D conversion unit that includes a plurality of channels and has a sequential conversion function, an A/D conversion period corresponding to three phases in a section during which the lower arm of the PWM signal of the motor control power module 906 is ON is necessary in order to perform motor current detection for three phases sequentially in the A/D conversion unit 920 in the motor control microcomputer 907. However, by applying the two-phase selection control method of Patent Reference 1 to motor current detection, the three phase motor currents can be obtained from the two phase motor currents. This enables the three-shunt sensorless sinusoidal motor drive control apparatus 900 provided with an A/D conversion unit that includes a plurality of channels and has a sequential conversion function, to perform motor current detection in an A/D conversion period corresponding to two phases in a section during which the lower arm of the PWM signal of the motor control power module 906 is ON.
However, in the conventional A/D conversion unit that includes a plurality of channels and has a sequential conversion function as shown in FIG. 3, a plurality of analog signals inputted into a plurality of input channels are sequentially converted in channel number order. Therefore, even when the two-phase selection control method of Patent Reference 1 is applied to motor current detection, the two phases for obtaining the correct motor currents need to correspond to adjacent channel numbers, so that it is impossible to arbitrarily select two out of the three consecutive phases to perform A/D conversion. That is, motor current detection cannot be performed within an A/D conversion period corresponding to two phases in a section during which the lower arm of the PWM signal of the motor control power module 906 is ON, but requires an A/D conversion period corresponding to three phases.
This is described in more detail below.
In the three-shunt sensorless sinusoidal motor drive control apparatus 900 that performs motor current detection for three phases sequentially in the A/D conversion unit 920 having one A/D converter 9201 by using the two-phase selection control method of Patent Document 1, the three phase motor currents detected in the shunt resistors 908 are amplified and the amplified motor current values are inputted into the A/D conversion unit 920 as analog input signals.
It is assumed here that the analog input signals are inputted into the input channels ADch1, ADch2, and ADch3 in the A/D conversion unit 920, with the input channels ADch1 and ADch3 corresponding to the two phases for obtaining the correct current values.
In theory, the A/D conversion unit 920 can correctly obtain the three phase motor currents for driving the sinusoidal drive three-phase motor 905, by performing A/D conversion of only the two input channels ADch1 and ADch3. However, the sequential A/D conversion loop in the register unit 9204 in the A/D conversion unit 920 needs to be set as “ADch1→ADch2→ADch3 → . . . ” with ADch2 being included between ADch1 and ADch3. Therefore, even when the two-phase selection control method of Patent Reference 1 is used, a time for performing A/D conversion of an analog current value from the input channel ADch2 is necessary. Hence an A/D conversion period corresponding to three phases in a motor current obtainment timing section during which the lower arm of the PWM signal of the motor control power module 906 is ON is required, as in the case of performing motor current detection for three phases sequentially using one A/D converter. That is, the three phase motor currents cannot be detected within an A/D conversion period corresponding to two phases in a section during which the lower arm of the PWM signal of the motor control power module 906 is ON.
For example, when an A/D conversion period corresponding to one phase in the A/D converter 9201 in the A/D conversion unit 920 is 1 μs, an A/D conversion period of 3 μs is required in the A/D converter 9201 so that the motor control microcomputer 907 obtains the motor current values.
To address this, a method of providing, in the A/D conversion unit having the A/D converter described in Non-patent Reference 1, an array register for designating a channel that is subject to A/D conversion has been proposed.
In detail, a plurality of array registers are provided in the register unit 9204 in the A/D conversion unit 920 having the A/D converter described in Non-patent Reference 1. Each array register stores information designating any of the input channels ADch0 to ADch5. The control unit 9203 controls the multiplexer 9200, the A/D converter 9201, and the demultiplexer 9202 so that A/D conversion is sequentially performed on analog signals from the input channels ADch0 to ADch5 in order of addresses of the array registers. Thus, by providing the array registers in the register unit 9204 in the A/D conversion unit 920, the order in which the input channels ADch0 to ADch5 are submitted to A/D conversion can be set freely.
As described above, according to the sequential A/D conversion method using array registers, it is possible to select only the two phases for obtaining the correct current values and perform sequential A/D conversion in the two-phase selection control method.
Therefore, by employing the two-phase selection control method and the sequential A/D conversion method that uses array registers, the three-shunt sensorless sinusoidal motor drive control apparatus 900 provided with an A/D conversion unit that includes a plurality of channels and has a sequential conversion function can detect the three phase motor currents for driving the sinusoidal drive three-phase motor 905, in an A/D conversion period corresponding to two phases in a section during which the lower arm of the PWM signal of the motor control power module 906 is ON.
However, in the sequential A/D conversion method using array registers, the same number of array registers as the number of all input channels that can be subject to A/D conversion need to be provided in the register unit 9204 in the A/D conversion unit 920. This consumes a lot of register resources. For instance, when the number of all input channels that can be subject to A/D conversion is 16, register resources of 16×4 bits are necessary. This causes an increase in chip area of the motor control microcomputer 907, resulting in an increase in cost of the motor control microcomputer 907.